Cited Patent References¶
This chapter contains a partial list of the patents that have been reviewed by the WISHBONE steward and others. In the opinion of the steward, the WISHBONE System-on-Chip (SoC) Interconnection Architecture for Portable IP Cores does not infringe on any of these patents. However, the possibility exists that an integrated circuit device designed to the WISHBONE specification could infringe on the intellectual property rights of others. The user assumes all responsibility for determining if their WISHBONE design infringes on the rights of others. All of these documents contain information relevant to SoC design and integration. Noteworthy patents are marked with a ‘(*)’.
This list is maintained for three reasons. First, a public domain specification can’t depend on patented ideas (unless permission to use the patent is obtained). This is the list of documents that have been reviewed to see if WISHBONE infringes on any known patents. Second, it provides a starting point for IC designers and other researchers who need to know if a specific SoC design infringes on the rights of others. Third, the patent database is a wonderful place to learn how other people have solved similar SoC problems. Patent documents are very good in this regard, as they must fully describe how to reproduce an invention.
General Methods Relating to SoC¶
- Hartmann, Alfred C. - US Patent No. 6,096,091
- DYNAMICALLY RECONFIGURABLE LOGIC NETWORKS INTERCONNECTED BY FALL-THROUGH FIFOS FOR FLEXIBLE PIPELINE PROCESSING IN A SYSTEM-ON-A- CHIP
- Luk et al. - US Patent No. 5,790,839
- SYSTEM INTEGRATION OF DRAM MACROS AND LOGIC CORES IN A SINGLE CHIP ARCHITECTURE
- Luk et al. - US Patent No. 5,883,814
- SYSTEM-ON-CHIP LAYOUT COMPILATION
- Wingard et al. - US Patent No. 5,948,089
- FULLY-PIPELINED FIXED-LATENCY COMMUNICATIONS SYSTEM WITH A REAL TYPE DYNAMIC BANDWIDTH ALLOCATION.
- Wingard et al. - US Patent No. 6,182,183 B1
- COMMUNICATION SYSTEM AND METHOD WITH MULTILEVEL CONNECTION IDENTIFICATION
Methods Relating to SoC Testability¶
- Edwards, et al.- US Patent No. 6,298,394 B1 (*)
- SYSTEM AND METHOD FOR CAPTURING INFORMATION ON AN INTERCONNECT IN AN INTEGRATED CIRCUIT
- Flynn, David W. - US Patent No. 5,525,971
- INTEGRATED CIRCUIT
Methods Relating to Variable Clock Frequency¶
- Gandhi et al. - US Patent No. 6,185,691 B1
- CLOCK GENERATION
- Kardach et al. - US Patent No. 5,473,767
- METHOD AND APPARATUS FOR ASYNCHRONOUSLY STOPPING THE CLOCK ON A PROCESSOR.
- Kardach et al. - US Patent No. 5,918,043
- METHOD AND APPARATUS FOR ASYNCHRONOUSLY STOPPING THE CLOCK ON A PROCESSOR.
- Maitra, Amit K. - US Patent No. 5,623,647
- APPLICATION SPECIFIC CLOCK THROTTLING
- Orton et al. - US Patent No. 6,118,306 (*)
- CHANGING CLOCK FREQUENCY
- Poplingher et al. - US Patent No. 6,173,379 B1
- MEMORY DEVICE FOR A MICROPROCESSOR REGISTER FILE HAVING A POWER MANAGEMENT SCHEME AND METHOD FOR COPYING INFORMATION BETWEEN MEMORY SUB-CELLS IN A SINGLE CLOCK CYCLE
- Stinson et al. - US Patent No. 6,127,858
- METHOD AND APPARATUS FOR VARYING A CLOCK FREQUENCY ON A PHASE BY PHASE BASIS
- Thomas, Thomas P. - US Patent No. 6,140,883
- TUNABLE, ENERGY EFFICIENT CLOCKING SCHEME
- Wong et al. - US Patent No. 5,586,307
- METHOD AND APPARATUS SUPPLYING SYNCHRONOUS CLOCK SIGNALS TO CIRCUIT COMPONENTS
- Young, Bruce - US Patent No. 6,079,022
- METHOD AND APPARATUS FOR DYNAMICALLY ADJUSTING THE CLOCK SPEED OF A BUS DEPENDING ON BUS ACTIVITY
Methods Relating to Selection of IP Cores¶
- Lee et al. - US Patent No. 6,102,961
- METHOD AND APPARATUS FOR SELECTING IP BLOCKS
Methods Relating to Data Flow Architectures¶
- Cismas, Sorin C. - US Patent No. 6,145,073
- DATA FLOW INTEGRATED CIRCUIT ARCHITECTURE
Methods Relating to Crossbar Switch Architectures¶
- Brewer et al. - US Patent No. 5,577,204
- PARALLEL PROCESSING COMPUTER SYSTEM INTERCONNECTIONS UTILIZING UNIDIRECTIONAL COMMUNICATION LINKS WITH SEPARATE REQUEST AND RESPONSE LINES FOR DIRECT COMMUNICATION OR USING A CROSSBAR SWITCHING DEVICE
- Nelson et al. - US Patent No. 6,138,185
- HIGH PERFORMANCE CROSSBAR SWITCH
- Van Krevelen et al. - US Patent No. 6,230,229 B1
- METHOD AND SYSTEM FOR ARBITRATING PATH CONTENTION IN A CROSSBAR INTERCONNECT NETWORK